VHDL & Verilog

[Etienne Bergeron <bergeret@iro.umontreal.ca>]

	We want to use a VHDL and Verilog parser written using SableCC. 
If we can't find one, we'll write it. But if someone is already working on 
such a project, we could join the effort.

Thank you,

-- 
Bergeron Etienne
Laboratoire de compilation et traitement parallele
Universite de Montreal 
http://www.iro.umontreal.ca/~bergeret
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         Black holes occur when God divides by zero.